During debug or a test of a semiconductor, engineers often take snapshots of a circuit that is under test. The snapshots provide insight into the current state of the device and may help to identify a problem by evaluating the data. In order to read out the values of circuit nodes, a circuit needs a way to send these values from latches or other storage devices in the circuit to the outside world. Scannable latches are often used. Previous scannable latches have used a plurality of clock signals to clock data and to implement the scan function. A disadvantage of the prior scannable latches is that the use of multiple clocks requires more power to implement and more signal conductors. Therefore, the implementation of scannable latches was inefficient either from power or size standpoints, or both. Additionally, in integrated circuits that have only a single clock, such multiple clock scannable latches are not useful.
Additionally, known latch circuits typically require careful transistor sizing in order to ensure reliable updating of values in the latch. Without the proper transistor size ratios, a new data value that is opposite from a previously stored value may not be reliably stored.
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